Symposium on AI Security at the Edge

Overview

The symposium aims to showcase research on AI security at the edge previously conducted at University of Glasgow in partnership with STMicroelectronics. This one-day event is expected to strengthen existing collaborations, seek new industry and academic collaborations leading to further research ideas, opportunities and fundings, enable knowledge exchange and sharing of specialised skills related to secure AI, provide proof-of-concept and feasibility of theoretical research by practical demonstration and getting feedback for further research.

Programme

09:00 - 10:00
Arrival and registration

10:00 - 10:15
Introduction
Dr Ferheen Ayaz (City St George's, University of London)

10:15 - 10:30
Welcome and opening remarks
Prof Raj Roy (City St George's, University of London)

10:30 - 12:00
Keynote speech and 30 mins Q&A
Dr Jose Cano Reyes (University of Glasgow)

12:00 - 13:00
Lunch break

13:00 - 14:30
Demonstrations and 30 mins Q&A

14:30 - 15:00
Afternoon break

15:00 - 16:30
Keynote speech and 30 mins Q&A
Danilo Pau (ST Microelectronics)

16:30 - 17:00
Group photo and closing remarks

17:00 - 19:00
Networking

Speakers

Dr Jose Cano Reyes

Jose is an Associate Professor in the School of Computing Science at the University of Glasgow, where he leads the Glasgow Intelligent Computing Laboratory (gicLAB) within the Systems Research Section (GLASS) and is also deputy Head of GLASS. His research interests are in the broad areas of Computer Architecture, Computer Systems, Compilers, Machine Learning, and Security.

His current research is mainly focused on Hardware/Software co-design approaches to efficiently and securely deploy AI/ML applications on resource-constrained edge devices. José is currently Principal Investigator at the University of Glasgow on the EU’s Horizon Europe project dAIEDGE and the UKRI APRIL AI Hub project SECDA-DSE, and Co-Investigator on the UKRI project IDEAL.

He was Principal Investigator on the UK’s PETRAS project MAISE, and Co-Investigator on the UKRI "Digital Security by Design" projects AppControl and Morello-HAT. He has obtained >£550K as a project PI, >£1.3M as a project Co-I, and >£81K from eight personal grants.

Jose received his Ph.D. in Computer Science from Universitat Politècnica de València (Spain) in January 2012. After that he was a Postdoctoral Researcher in the Department of Computer Architecture at Universitat Politècnica de Catalunya (Spain) until December 2013. Then he joined the Institute for Computing Systems Architecture in the School of Informatics at The University of Edinburgh (UK) where he was a Research Associate between January 2014 and August 2018. He is a senior member of the IEEE and ACM research societies and a member of the HiPEAC, dAIEDGE and PETRAS networks of excellence.

Mr Danilo Pau

Danilo spent 32 years in STMicroelectronics and in System R&D. His (source GoogleScholar) h-index is 30, i10-index 86. He produced 109 invention’s requests, 80 EU and 71 US application patents. He is author of 224 scientific publications, 113 (2012-2015) ISO/IEC/MPEG input&output documents and had 132 invited talks including key notes, seminars, tutorials at Universities/Conferences (to date). He graduated on Electronic Engineering in 1992 at Politecnico di Milano after one year internship in SGS-THOMSON/CASA on 50% memory reduced HD-MAC HW decoder.

He has got a background on MPEG2 video memory reduction (SD/HD), video (up to H.264) encoding, transcoding, OpenVG/OpenGL-ES since Khronos was established; he co-chaired ISO/IEC SC29-WG11 CDVS and CDVA for 3 years, computer vision and tiny AI since 2016 (through the release of the 2024 Unified AI Core Technology) now part of STM32CubeMX, Stellar-Studio, SPC-Studio.AI, MEMs Studio, STM32 Developer Cloud and the Suite.

On 2019 he was elevated IEEE Fellow; on 2022 AAIA Fellow, APSIPA life member since 2020, Sigma Xi honor society (invited) member since 2024. He served as Industry Ambassador (Italy section), coordinator IEEE Region 8 South Europe, vice-chairman of the “Intelligent Cyber-Physical Systems” Task Force IEEE CIS, IEEE R8 AfI internship initiative , AE IEEE TNNLS, Member of the IEEE CTSoc MDAI, 2023 IEEE CS Fellow EVM.

He personally curated all the way the IEEE Milestone on Multiple Silicon Technologies on a chip, 1985 ratified by IEEE/2021, and IEEE Milestone on MPEG Multimedia Integrated Circuits, 1984-1993, ratified IEEE/2022, Integrated Circuits for Satellite Digital Radio, 1996-1997, ratified IEEE/2024. He serves TinyML (now EdgeAi) Foundation (Symposium, Summit, EMEA), chair of the TinyML on Device Learning, co-founded AutoTinyML, co-chair TinyML Talks and chair of Edge GenAI working group.

He is co-chair of EdgeAI Research track at EdgeAI Austin 2025. Coordinating contributions to MPAI standardization on neural network watermarking. He was awarded with my team "Finmeccanica Innovation Award 2004 Embedded 3D graphics", STAR Gold award 2014 for high performing Technical Staff (which I co-funded), best demo award with Politecnico di Milano on MPEG Visual Search, on 2014, STAR Silver award on 2019 for STM32Cube.AI, 2020 Spring APSIPA Industrial Distinguished Leaders Award, STAR Innovation Award in 2023, Career Achievement Award by EdgeAI Foundation on 2024.

He supervised countless students over 30+ years and strongly and openly cooperated with many professors, professionals, researchers, and loves continuing that. Innovation and be part of a scientific community are his needs.

Abstracts

Dr Jose Cano Reyes' abstract: Next-Gen Edge AI: Enhancing Performance and Security

Deep Neural Networks (DNNs) are increasingly a key component within Artificial Intelligence (AI) applications for a number of domains, including computer vision, natural language processing, and scientific computing.

At the same time, executing DNN models on edge devices may allow secure computation and lower energy consumption and cost, but to become practical performance must improve dramatically and security must be guaranteed. This is due to the significant demands introduced by emerging DNN models in terms of both memory and compute and the reduce availability of them in constrained edge devices.

In this talk I will introduce the Glasgow Intelligent Computing Laboratory (gicLAB) and give an overview of our current and future research, with an emphasis on approaches to efficiently and securely deploy and run AI/ML applications on constrained edge devices.

Mr Danilo Pau's abstract: Design and Deployment of Deeply Quantized Neural Networks for Edge Computing

Minimize memory footprint, maximize computational efficiency and accuracy are great challenges and require many efforts when devising low bit-depth neural network. They are particularly aimed for EdgeAI solution, leveraging wide availability of sensors and microcontroller.

Deeply Quantized Neural Networks (DQNNs) offer the most interesting approach for saving memory and complexity. However, the design and the training of DQNN also is not a trivial task. This is also complicated since current off-the-shelf microcontrollers are not yet able to exploit their potentialities, lacking dedicated instructions. A new generation of sensors, with integrated computing capability instead offers new meanings and perspectives to DQNN exploitation.

Furthermore, a Machine Learning practitioner eager to learn how to design DQNN shall use an experimental deep learning tool such as QKeras to achieve interesting accuracies compared to more traditional design approaches. They also requires tools to automatically deploy DQNN solutions on sensors and micro controllers at an un precedented productivity level.

In this session all those aspects will be discussed and demonstrated with reference to latest efforts of ST including a) learning QKeras and b) ST EdgeAI Core Technology tool for efficient DQNN deployment on sensors and micro controllers. It will include associated demo and code inspection.